MC9S12XF512MLM

MC9S12XF512MLM  Description

Based around an enhanced S12X core, the MC9S12XF-Family runs 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12XF-Family also features a new flexible interrupt handler, which allows multilevel nested interrupts. The MC9S12XF-Family features the performance-boosting enhanced XGATE co-processor. The XGATE is programmable in the “C” language and runs at twice the bus frequency of the S12. The XGATE instruction

set is optimized for data movement, logic, and bit manipulation instructions. Any peripheral module can be serviced by the XGATE.

The MC9S12XF-Family features a Memory Protection Unit (MPU). The MC9S12XF-Family features a FlexRay module for high-speed serial communication supporting various bit rates up to 10 Mbit/s. The FlexRay internal clock can be generated from crystals ranging from 4MHz to 40MHz1. The 64-pin LQFP allows interfacing to a single FlexRay channel. The 64-pin LQFP (10mm x 10mm) is intended for those applications challenged by the size constraint of some satellite FlexRay modules. The 112-pin LQFP offers an increase in the number of I/Os as well as 16 A/D channels. In addition to that, the 144-pin LQFP provides a full 16-bit wide non-multiplexed external bus interface with the pins usable as general purpose I/O in single-chip modes.

MC9S12XF512MLM  Features

16-Bit CPU12X

— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed.

— Enhanced indexed addressing

— Additional (superset) instructions to improve 32-bit calculations and semaphore handling

— Access large data segments independent of PPAGE

Enhanced Interrupt Module

— Eight levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level

— One non-maskable high priority interrupt (XIRQ)

— Wake-up Interrupt Inputs

Memory Protection Unit (MPU)

— 4 address regions definable per active program task

— Address range granularity as low as 256 bytes

— Protection Attributes

– No write

– No execute

— Non-maskable interrupt on access violation

XGATE

— Programmable, high-performance I/O coprocessor module – up to 100 MIPS RISC performance

— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

— Performs logical, shifts, arithmetic, and bit operations on data

— Can interrupt the HCS12X CPU signaling transfer completion

— Triggers from any hardware module as well as from the CPU are possible

— Two interrupt levels to service high-priority tasks

— Enables Full CAN capability when used in conjunction with the MSCAN module