MPC857DSLVR50B
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- Mfr.Part #
- MPC857DSLVR50B
- Manufacturer
- Freescale Semiconductor
- Package / Case
- 357-BBGA
- Datasheet
- Download
- Description
- POWERQUICC RISC MICROPROCESSOR
- Stock
- 15
- In Stock ：
- 15
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- Manufacturer :
- Freescale Semiconductor
- Product Category :
- Microprocessors
- Core Processor :
- MPC8xx
- Speed :
- 50MHz
- Supplier Device Package :
- 357-PBGA (25x25)
- Number of Cores/Bus Width :
- 1 Core, 32-Bit
- Display & Interface Controllers :
- -
- Co-Processors/DSP :
- Communications; CPM
- RAM Controllers :
- DRAM
- USB :
- -
- Security Features :
- -
- Package / Case :
- 357-BBGA
- SATA :
- -
- Operating Temperature :
- 0°C ~ 105°C (TA)
- Product Status :
- Active
- Voltage - I/O :
- 3.3V
- Graphics Acceleration :
- No
- Ethernet :
- 10Mbps (1), 10/100Mbps (1)
- Datasheets
- MPC857DSLVR50B
MPC8xx Microprocessor MPC8xx Series 357-BBGA
MPC857DSLVR50B Description
The MPC862/857T/857DSL is a derivative of Freescale’s MPC860 PowerQUICC? family of devices. It is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC862/857T/857DSL provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family.
MPC857DSLVR50B Features
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
– 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte
instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative
with 128 sets.
– 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data
cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
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